==================================================================================================== SCENARIO null (seed 5). Planted size per bin = median over alive units of the planted per-unit size (deg per readout). planted kick: 0 everywhere reach ibm_fez job SYNTH-null-5 plan SYNTH coherence: N=0 baseline median 0.617 (all 156 qubits); N=8 idle median 0.620, readout median 0.601; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 1 of 38, d=5 1 of 39, d=6 1 of 38, d=7 2 of 38, d>=8 4 of 88, d<=2 0 of 68 RR0 kick per readout, all untouched units, all layouts +0.003663 [-0.02005, +0.01851] deg n=342 -> CONSISTENT (copy gap -0.02041 [-0.04655, +0.0446]) RR1 kick size at d=3 +0.03755 [-0.04444, +0.09537] deg n=42 -> CONSISTENT (copy gap +0.09768 [-0.003722, +0.1693]) RR1 kick size at d=4 -0.04292 [-0.08756, +0.01147] deg n=37 -> CONSISTENT (copy gap -0.04655 [-0.1484, +0.1219]) RR1 kick size at d=5 +0.008615 [-0.02815, +0.06294] deg n=38 -> CONSISTENT (copy gap -0.04492 [-0.168, +0.04736]) RR1 kick size at d=6 -0.01688 [-0.08179, +0.04343] deg n=37 -> CONSISTENT (copy gap -0.03253 [-0.1689, +0.2983]) RR1 kick size at d=7 -0.01085 [-0.1245, +0.1285] deg n=36 -> CONSISTENT (copy gap +0.07477 [-0.1713, +0.1594]) RR1 kick size at d>=8 +0.005648 [-0.03299, +0.02916] deg n=84 -> CONSISTENT (copy gap -0.04429 [-0.1735, +0.003665]) RR2 size(d=3) - size(d=4) +0.08047 [-0.008767, +0.148] deg -> CONSISTENT (copy gap +0.1442 [-0.06135, +0.2648]) RR2 size(d=4) - size(d=5) -0.05154 [-0.1334, +0.01912] deg -> CONSISTENT (copy gap -0.001626 [-0.1193, +0.2225]) RR2 size(d=5) - size(d=6) +0.02549 [-0.04889, +0.122] deg -> CONSISTENT (copy gap -0.01239 [-0.3635, +0.1285]) RR2 size(d=6) - size(d=7) -0.006028 [-0.1837, +0.1285] deg -> CONSISTENT (copy gap -0.1073 [-0.2312, +0.3175]) RR2 size(d=7) - size(d>=8) -0.0165 [-0.14, +0.1353] deg -> CONSISTENT (copy gap +0.1191 [-0.1279, +0.2665]) RR3 this chip: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size +0.038 [-0.044, +0.095] deg (the bound) (bins in order: d=3 CONSISTENT, d=4 CONSISTENT, d=5 CONSISTENT, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) reach ibm_kingston job SYNTH-null-5 plan SYNTH coherence: N=0 baseline median 0.613 (all 156 qubits); N=8 idle median 0.615, readout median 0.596; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 0 of 38, d=5 0 of 39, d=6 0 of 38, d=7 1 of 38, d>=8 2 of 88, d<=2 1 of 68 RR0 kick per readout, all untouched units, all layouts -0.01587 [-0.04695, +0.01462] deg n=347 -> CONSISTENT (copy gap +0.01056 [-0.03728, +0.06166]) RR1 kick size at d=3 -0.01183 [-0.09512, +0.04362] deg n=42 -> CONSISTENT (copy gap -0.02617 [-0.1564, +0.09765]) RR1 kick size at d=4 +0.002629 [-0.04053, +0.07622] deg n=38 -> CONSISTENT (copy gap -0.006625 [-0.1132, +0.1968]) RR1 kick size at d=5 +0.0678 [-0.02093, +0.1466] deg n=39 -> CONSISTENT (copy gap -0.03934 [-0.1297, +0.1433]) RR1 kick size at d=6 +0.01294 [-0.04831, +0.0898] deg n=38 -> CONSISTENT (copy gap +0.08082 [-0.07362, +0.1742]) RR1 kick size at d=7 -0.006196 [-0.1123, +0.0803] deg n=37 -> CONSISTENT (copy gap +0.04785 [-0.005074, +0.1225]) RR1 kick size at d>=8 +0.04441 [-0.02658, +0.07313] deg n=86 -> CONSISTENT (copy gap -0.08329 [-0.1559, +0.03439]) RR2 size(d=3) - size(d=4) -0.01446 [-0.1251, +0.06194] deg -> CONSISTENT (copy gap -0.01955 [-0.2517, +0.1637]) RR2 size(d=4) - size(d=5) -0.06517 [-0.1514, +0.05317] deg -> CONSISTENT (copy gap +0.03272 [-0.1673, +0.2274]) RR2 size(d=5) - size(d=6) +0.05486 [-0.04596, +0.1614] deg -> CONSISTENT (copy gap -0.1202 [-0.2559, +0.108]) RR2 size(d=6) - size(d=7) +0.01914 [-0.09714, +0.1467] deg -> CONSISTENT (copy gap +0.03297 [-0.1308, +0.1459]) RR2 size(d=7) - size(d>=8) copies shifted -> CANNOT TELL (copy gap of the difference +0.1311 [+0.00699, +0.2337]) RR3 this chip: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size -0.012 [-0.095, +0.044] deg (the bound) (bins in order: d=3 CONSISTENT, d=4 CONSISTENT, d=5 CONSISTENT, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) reach ibm_marrakesh job SYNTH-null-5 plan SYNTH coherence: N=0 baseline median 0.636 (all 156 qubits); N=8 idle median 0.629, readout median 0.616; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 0 of 38, d=5 0 of 39, d=6 1 of 38, d=7 0 of 38, d>=8 2 of 88, d<=2 1 of 68 RR0 kick per readout, all untouched units, all layouts -0.01817 [-0.03851, +0.003149] deg n=347 -> CONSISTENT (copy gap -0.002848 [-0.04049, +0.02702]) RR1 kick size at d=3 +0.01966 [-0.04277, +0.1063] deg n=42 -> CONSISTENT (copy gap +0.005878 [-0.09258, +0.128]) RR1 kick size at d=4 +0.044 [-0.01872, +0.07898] deg n=38 -> CONSISTENT (copy gap +0.05262 [-0.1081, +0.1603]) RR1 kick size at d=5 +0.01477 [-0.05983, +0.0861] deg n=39 -> CONSISTENT (copy gap +0.001822 [-0.1028, +0.1426]) RR1 kick size at d=6 +0.02403 [-0.04968, +0.05989] deg n=37 -> CONSISTENT (copy gap -0.05176 [-0.1335, +0.06279]) RR1 kick size at d=7 +0.01735 [-0.06771, +0.04448] deg n=38 -> CONSISTENT (copy gap +0.002971 [-0.09944, +0.1427]) RR1 kick size at d>=8 +0.01472 [-0.04302, +0.0575] deg n=86 -> CONSISTENT (copy gap +0.0129 [-0.044, +0.1174]) RR2 size(d=3) - size(d=4) -0.02434 [-0.09358, +0.08551] deg -> CONSISTENT (copy gap -0.04674 [-0.1791, +0.1741]) RR2 size(d=4) - size(d=5) +0.02923 [-0.06478, +0.1125] deg -> CONSISTENT (copy gap +0.0508 [-0.1873, +0.1934]) RR2 size(d=5) - size(d=6) -0.009259 [-0.09626, +0.07825] deg -> CONSISTENT (copy gap +0.05358 [-0.1259, +0.2334]) RR2 size(d=6) - size(d=7) +0.006681 [-0.05705, +0.1048] deg -> CONSISTENT (copy gap -0.05473 [-0.2275, +0.1237]) RR2 size(d=7) - size(d>=8) +0.002631 [-0.08821, +0.06321] deg -> CONSISTENT (copy gap -0.009927 [-0.1607, +0.1439]) RR3 this chip: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size +0.020 [-0.043, +0.106] deg (the bound) (bins in order: d=3 CONSISTENT, d=4 CONSISTENT, d=5 CONSISTENT, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) RR0 kick per readout, all untouched units, all layouts combined -0.008063 [-0.02092, +0.004794] -> CONSISTENT | chip-to-chip spread chi2/dof 1.29 (dof 2) RR1 kick size at d=3 combined +0.01479 [-0.02629, +0.05588] -> CONSISTENT | chip-to-chip spread chi2/dof 0.49 (dof 2) RR1 kick size at d=4 combined +0.001519 [-0.02836, +0.03139] -> CONSISTENT | chip-to-chip spread chi2/dof 3.00 (dof 2) RR1 kick size at d=5 combined +0.02042 [-0.01466, +0.05551] -> CONSISTENT | chip-to-chip spread chi2/dof 0.76 (dof 2) RR1 kick size at d=6 combined +0.008039 [-0.02736, +0.04344] -> CONSISTENT | chip-to-chip spread chi2/dof 0.48 (dof 2) RR1 kick size at d=7 combined +0.008537 [-0.03673, +0.0538] -> CONSISTENT | chip-to-chip spread chi2/dof 0.14 (dof 2) RR1 kick size at d>=8 combined +0.01611 [-0.007242, +0.03946] -> CONSISTENT | chip-to-chip spread chi2/dof 0.84 (dof 2) RR2 size(d=3) - size(d=4) combined +0.02093 [-0.02896, +0.07081] -> CONSISTENT | chip-to-chip spread chi2/dof 1.87 (dof 2) RR2 size(d=4) - size(d=5) combined -0.02882 [-0.07914, +0.02151] -> CONSISTENT | chip-to-chip spread chi2/dof 1.24 (dof 2) RR2 size(d=5) - size(d=6) combined +0.02042 [-0.03218, +0.07303] -> CONSISTENT | chip-to-chip spread chi2/dof 0.44 (dof 2) RR2 size(d=6) - size(d=7) combined +0.007893 [-0.05399, +0.06978] -> CONSISTENT | chip-to-chip spread chi2/dof 0.03 (dof 2) RR2 size(d=7) - size(d>=8) combined -0.001812 [-0.06815, +0.06452] -> CONSISTENT | chip-to-chip spread chi2/dof 0.06 (dof 1) RR3 combined: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size +0.015 [-0.026, +0.056] deg (the bound) (bins in order: d=3 CONSISTENT, d=4 CONSISTENT, d=5 CONSISTENT, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) TRUTH fez: d=3 +0.000 d=4 +0.000 d=5 +0.000 d=6 +0.000 d=7 +0.000 d>=8 +0.000 TRUTH kingston: d=3 +0.000 d=4 +0.000 d=5 +0.000 d=6 +0.000 d=7 +0.000 d>=8 +0.000 TRUTH marrakesh: d=3 +0.000 d=4 +0.000 d=5 +0.000 d=6 +0.000 d=7 +0.000 d>=8 +0.000 COMBINED vs mean planted: d=3 truth +0.000 read +0.015 [-0.026, +0.056] CONSISTENT covers | d=4 truth +0.000 read +0.002 [-0.028, +0.031] CONSISTENT covers | d=5 truth +0.000 read +0.020 [-0.015, +0.056] CONSISTENT covers | d=6 truth +0.000 read +0.008 [-0.027, +0.043] CONSISTENT covers | d=7 truth +0.000 read +0.009 [-0.037, +0.054] CONSISTENT covers | d>=8 truth +0.000 read +0.016 [-0.007, +0.039] CONSISTENT covers ==================================================================================================== SCENARIO step (seed 5). Planted size per bin = median over alive units of the planted per-unit size (deg per readout). planted kick: -2.0 deg for d<=5, 0 beyond (x per-unit spread) reach ibm_fez job SYNTH-step-5 plan SYNTH coherence: N=0 baseline median 0.617 (all 156 qubits); N=8 idle median 0.620, readout median 0.603; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 1 of 38, d=5 1 of 39, d=6 1 of 38, d=7 2 of 38, d>=8 4 of 88, d<=2 0 of 68 RR0 kick per readout, all untouched units, all layouts -1.075 [-1.336, -0.3286] deg n=342 -> BELOW (copy gap -0.002827 [-0.04116, +0.04383]) RR1 kick size at d=3 copies shifted -0.09228 [-0.1765, -0.002183] | copy0 +2.208 copy1 +2.324 -> CANNOT TELL RR1 kick size at d=4 +2.001 [+1.669, +2.661] deg n=37 -> ABOVE (copy gap -0.04127 [-0.1957, +0.08791]) RR1 kick size at d=5 +2.193 [+1.654, +2.501] deg n=38 -> ABOVE (copy gap +0.06464 [-0.0677, +0.203]) RR1 kick size at d=6 +0.01688 [-0.04343, +0.08179] deg n=37 -> CONSISTENT (copy gap +0.03253 [-0.2983, +0.1689]) RR1 kick size at d=7 +0.01085 [-0.127, +0.1251] deg n=36 -> CONSISTENT (copy gap -0.07477 [-0.1594, +0.1713]) RR1 kick size at d>=8 -0.005648 [-0.03064, +0.03396] deg n=84 -> CONSISTENT (copy gap +0.04429 [-0.003665, +0.1712]) RR2 size(d=3) - size(d=4) copies shifted -> CANNOT TELL (copy gap of the difference -0.05101 [-0.1935, +0.1216]) RR2 size(d=4) - size(d=5) -0.1918 [-0.6643, +0.6797] deg -> CONSISTENT (copy gap -0.1059 [-0.3056, +0.06957]) RR2 size(d=5) - size(d=6) +2.176 [+1.613, +2.492] deg -> ABOVE (copy gap +0.03211 [-0.132, +0.3811]) RR2 size(d=6) - size(d=7) +0.006028 [-0.1344, +0.1872] deg -> CONSISTENT (copy gap +0.1073 [-0.3455, +0.2437]) RR2 size(d=7) - size(d>=8) +0.0165 [-0.1343, +0.1381] deg -> CONSISTENT (copy gap -0.1191 [-0.2565, +0.1321]) RR3 this chip: reach edge (unbroken ABOVE from d=3) d=5; first bin past it d=6 CONSISTENT, size +0.017 [-0.043, +0.082] deg (the bound) (bins in order: d=3 CANNOT TELL, d=4 ABOVE, d=5 ABOVE, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) reach ibm_kingston job SYNTH-step-5 plan SYNTH coherence: N=0 baseline median 0.613 (all 156 qubits); N=8 idle median 0.615, readout median 0.596; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 0 of 38, d=5 0 of 39, d=6 0 of 38, d=7 1 of 38, d>=8 2 of 88, d<=2 1 of 68 RR0 kick per readout, all untouched units, all layouts -1.029 [-1.271, -0.3198] deg n=347 -> BELOW (copy gap -0.01742 [-0.05039, +0.02905]) RR1 kick size at d=3 +2.06 [+1.803, +2.506] deg n=42 -> ABOVE (copy gap -0.001096 [-0.1357, +0.07711]) RR1 kick size at d=4 +2.451 [+1.874, +2.817] deg n=38 -> ABOVE (copy gap -0.001757 [-0.162, +0.1847]) RR1 kick size at d=5 +2.098 [+1.709, +2.516] deg n=39 -> ABOVE (copy gap +0.09075 [-0.01031, +0.1788]) RR1 kick size at d=6 +0.01294 [-0.04717, +0.08112] deg n=38 -> CONSISTENT (copy gap +0.08082 [-0.07298, +0.1869]) RR1 kick size at d=7 -0.006196 [-0.1123, +0.0803] deg n=37 -> CONSISTENT (copy gap +0.04785 [-0.005074, +0.1225]) RR1 kick size at d>=8 +0.04441 [-0.02395, +0.07313] deg n=86 -> CONSISTENT (copy gap -0.08329 [-0.1559, +0.02542]) RR2 size(d=3) - size(d=4) -0.3909 [-0.8746, +0.286] deg -> CONSISTENT (copy gap +0.0006606 [-0.2346, +0.1712]) RR2 size(d=4) - size(d=5) +0.3534 [-0.3977, +0.8351] deg -> CONSISTENT (copy gap -0.09251 [-0.2709, +0.13]) RR2 size(d=5) - size(d=6) +2.085 [+1.74, +2.537] deg -> ABOVE (copy gap +0.009925 [-0.1458, +0.1819]) RR2 size(d=6) - size(d=7) +0.01914 [-0.09706, +0.1479] deg -> CONSISTENT (copy gap +0.03297 [-0.1141, +0.1459]) RR2 size(d=7) - size(d>=8) copies shifted -> CANNOT TELL (copy gap of the difference +0.1311 [+0.005771, +0.231]) RR3 this chip: reach edge (unbroken ABOVE from d=3) d=5; first bin past it d=6 CONSISTENT, size +0.013 [-0.047, +0.081] deg (the bound) (bins in order: d=3 ABOVE, d=4 ABOVE, d=5 ABOVE, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) reach ibm_marrakesh job SYNTH-step-5 plan SYNTH coherence: N=0 baseline median 0.636 (all 156 qubits); N=8 idle median 0.629, readout median 0.616; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 0 of 38, d=5 0 of 39, d=6 1 of 38, d=7 0 of 38, d>=8 2 of 88, d<=2 1 of 68 RR0 kick per readout, all untouched units, all layouts -0.816 [-1.14, -0.2733] deg n=347 -> BELOW (copy gap -0.005475 [-0.04347, +0.02223]) RR1 kick size at d=3 +2.057 [+1.616, +2.368] deg n=42 -> ABOVE (copy gap -0.05518 [-0.167, +0.1068]) RR1 kick size at d=4 +1.712 [+1.48, +2.106] deg n=38 -> ABOVE (copy gap +0.04756 [-0.07267, +0.2033]) RR1 kick size at d=5 +1.93 [+1.622, +2.294] deg n=39 -> ABOVE (copy gap +0.01462 [-0.07206, +0.2076]) RR1 kick size at d=6 +0.02403 [-0.04968, +0.05989] deg n=37 -> CONSISTENT (copy gap -0.05176 [-0.1335, +0.0965]) RR1 kick size at d=7 +0.01735 [-0.06771, +0.0434] deg n=38 -> CONSISTENT (copy gap +0.002971 [-0.1013, +0.1428]) RR1 kick size at d>=8 +0.01472 [-0.04337, +0.05546] deg n=86 -> CONSISTENT (copy gap +0.0129 [-0.044, +0.1174]) RR2 size(d=3) - size(d=4) +0.3451 [-0.3308, +0.7437] deg -> CONSISTENT (copy gap -0.1027 [-0.3173, +0.08608]) RR2 size(d=4) - size(d=5) -0.218 [-0.5966, +0.3222] deg -> CONSISTENT (copy gap +0.03293 [-0.2047, +0.2206]) RR2 size(d=5) - size(d=6) +1.906 [+1.576, +2.281] deg -> ABOVE (copy gap +0.06638 [-0.1029, +0.2985]) RR2 size(d=6) - size(d=7) +0.006681 [-0.05391, +0.1072] deg -> CONSISTENT (copy gap -0.05473 [-0.2277, +0.1196]) RR2 size(d=7) - size(d>=8) +0.002631 [-0.09113, +0.06449] deg -> CONSISTENT (copy gap -0.009927 [-0.1673, +0.1469]) RR3 this chip: reach edge (unbroken ABOVE from d=3) d=5; first bin past it d=6 CONSISTENT, size +0.024 [-0.050, +0.060] deg (the bound) (bins in order: d=3 ABOVE, d=4 ABOVE, d=5 ABOVE, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) RR0 kick per readout, all untouched units, all layouts combined -0.9595 [-1.23, -0.6893] -> BELOW | chip-to-chip spread chi2/dof 0.35 (dof 2) RR1 kick size at d=3 combined +2.059 [+1.802, +2.316] -> ABOVE | chip-to-chip spread chi2/dof 0.00 (dof 1) RR1 kick size at d=4 combined +1.952 [+1.721, +2.182] -> ABOVE | chip-to-chip spread chi2/dof 3.31 (dof 2) RR1 kick size at d=5 combined +2.051 [+1.831, +2.272] -> ABOVE | chip-to-chip spread chi2/dof 0.49 (dof 2) RR1 kick size at d=6 combined +0.01859 [-0.01609, +0.05328] -> CONSISTENT | chip-to-chip spread chi2/dof 0.04 (dof 2) RR1 kick size at d=7 combined +0.01139 [-0.03357, +0.05635] -> CONSISTENT | chip-to-chip spread chi2/dof 0.09 (dof 2) RR1 kick size at d>=8 combined +0.01086 [-0.01276, +0.03448] -> CONSISTENT | chip-to-chip spread chi2/dof 1.43 (dof 2) RR2 size(d=3) - size(d=4) combined +0.005399 [-0.3888, +0.3996] -> CONSISTENT | chip-to-chip spread chi2/dof 3.33 (dof 1) RR2 size(d=4) - size(d=5) combined -0.05503 [-0.378, +0.268] -> CONSISTENT | chip-to-chip spread chi2/dof 1.16 (dof 2) RR2 size(d=5) - size(d=6) combined +2.035 [+1.809, +2.262] -> ABOVE | chip-to-chip spread chi2/dof 0.49 (dof 2) RR2 size(d=6) - size(d=7) combined +0.009784 [-0.0523, +0.07187] -> CONSISTENT | chip-to-chip spread chi2/dof 0.02 (dof 2) RR2 size(d=7) - size(d>=8) combined +0.006043 [-0.06152, +0.07361] -> CONSISTENT | chip-to-chip spread chi2/dof 0.03 (dof 1) RR3 combined: reach edge (unbroken ABOVE from d=3) d=5; first bin past it d=6 CONSISTENT, size +0.019 [-0.016, +0.053] deg (the bound) (bins in order: d=3 ABOVE, d=4 ABOVE, d=5 ABOVE, d=6 CONSISTENT, d=7 CONSISTENT, d>=8 CONSISTENT) TRUTH fez: d=3 +2.301 d=4 +2.039 d=5 +2.248 d=6 +0.000 d=7 +0.000 d>=8 +0.000 TRUTH kingston: d=3 +1.995 d=4 +2.319 d=5 +1.963 d=6 +0.000 d=7 +0.000 d>=8 +0.000 TRUTH marrakesh: d=3 +1.956 d=4 +1.700 d=5 +1.980 d=6 +0.000 d=7 +0.000 d>=8 +0.000 COMBINED vs mean planted: d=3 truth +2.084 read +2.059 [+1.802, +2.316] ABOVE covers | d=4 truth +2.020 read +1.952 [+1.721, +2.182] ABOVE covers | d=5 truth +2.064 read +2.051 [+1.831, +2.272] ABOVE covers | d=6 truth +0.000 read +0.019 [-0.016, +0.053] CONSISTENT covers | d=7 truth +0.000 read +0.011 [-0.034, +0.056] CONSISTENT covers | d>=8 truth +0.000 read +0.011 [-0.013, +0.034] CONSISTENT covers ==================================================================================================== SCENARIO smooth (seed 5). Planted size per bin = median over alive units of the planted per-unit size (deg per readout). planted kick: -3.0 x exp(-(d-1)/2.5) deg (x per-unit spread) reach ibm_fez job SYNTH-smooth-5 plan SYNTH coherence: N=0 baseline median 0.617 (all 156 qubits); N=8 idle median 0.620, readout median 0.602; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 1 of 38, d=5 1 of 39, d=6 1 of 38, d=7 2 of 38, d>=8 4 of 88, d<=2 0 of 68 RR0 kick per readout, all untouched units, all layouts -0.6189 [-0.7819, -0.5166] deg n=342 -> BELOW (copy gap -0.005849 [-0.03569, +0.03546]) RR1 kick size at d=3 copies shifted -0.1189 [-0.1624, -0.01693] | copy0 +1.429 copy1 +1.557 -> CANNOT TELL RR1 kick size at d=4 +0.9485 [+0.7977, +1.244] deg n=37 -> ABOVE (copy gap +0.006645 [-0.1619, +0.1459]) RR1 kick size at d=5 +0.5864 [+0.4795, +0.7108] deg n=38 -> ABOVE (copy gap +0.03412 [-0.0138, +0.1688]) RR1 kick size at d=6 +0.4512 [+0.2713, +0.6039] deg n=37 -> ABOVE (copy gap +0.0126 [-0.264, +0.1939]) RR1 kick size at d=7 +0.2606 [+0.09935, +0.3737] deg n=36 -> ABOVE (copy gap -0.04668 [-0.1529, +0.2154]) RR1 kick size at d>=8 +0.116 [+0.08315, +0.1755] deg n=84 -> ABOVE (copy gap +0.0363 [-0.02821, +0.1691]) RR2 size(d=3) - size(d=4) copies shifted -> CANNOT TELL (copy gap of the difference -0.1255 [-0.2775, +0.06708]) RR2 size(d=4) - size(d=5) +0.3621 [+0.1901, +0.6443] deg -> ABOVE (copy gap -0.02748 [-0.2501, +0.128]) RR2 size(d=5) - size(d=6) +0.1352 [-0.07962, +0.3235] deg -> CONSISTENT (copy gap +0.02152 [-0.1493, +0.3346]) RR2 size(d=6) - size(d=7) +0.1906 [-0.009069, +0.4179] deg -> CONSISTENT (copy gap +0.05929 [-0.3074, +0.2406]) RR2 size(d=7) - size(d>=8) +0.1446 [-0.02461, +0.2621] deg -> CONSISTENT (copy gap -0.08299 [-0.2408, +0.1676]) RR3 this chip: reach edge (unbroken ABOVE from d=3) d>=8; every bin to d>=8 resolved: the kick reaches past d=8 (bins in order: d=3 CANNOT TELL, d=4 ABOVE, d=5 ABOVE, d=6 ABOVE, d=7 ABOVE, d>=8 ABOVE) reach ibm_kingston job SYNTH-smooth-5 plan SYNTH coherence: N=0 baseline median 0.613 (all 156 qubits); N=8 idle median 0.615, readout median 0.596; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 0 of 38, d=5 0 of 39, d=6 0 of 38, d=7 1 of 38, d>=8 2 of 88, d<=2 1 of 68 RR0 kick per readout, all untouched units, all layouts -0.6537 [-0.7715, -0.5447] deg n=347 -> BELOW (copy gap +0.001144 [-0.04638, +0.05728]) RR1 kick size at d=3 +1.326 [+1.205, +1.673] deg n=42 -> ABOVE (copy gap -0.01823 [-0.09644, +0.07554]) RR1 kick size at d=4 +1.083 [+0.7499, +1.342] deg n=38 -> ABOVE (copy gap +0.01423 [-0.1626, +0.22]) RR1 kick size at d=5 +0.7273 [+0.6193, +0.8587] deg n=39 -> ABOVE (copy gap -0.003543 [-0.0864, +0.1766]) RR1 kick size at d=6 +0.4133 [+0.3512, +0.567] deg n=38 -> ABOVE (copy gap +0.0434 [-0.09288, +0.2438]) RR1 kick size at d=7 +0.2533 [+0.1309, +0.4311] deg n=37 -> ABOVE (copy gap +0.06157 [-0.04566, +0.1094]) RR1 kick size at d>=8 +0.1803 [+0.1494, +0.2232] deg n=86 -> ABOVE (copy gap -0.07404 [-0.1536, +0.04027]) RR2 size(d=3) - size(d=4) +0.2429 [-0.05563, +0.686] deg -> CONSISTENT (copy gap -0.03245 [-0.2449, +0.1703]) RR2 size(d=4) - size(d=5) +0.3561 [+0.01679, +0.6597] deg -> ABOVE (copy gap +0.01777 [-0.2343, +0.2212]) RR2 size(d=5) - size(d=6) +0.314 [+0.1038, +0.4783] deg -> ABOVE (copy gap -0.04695 [-0.2226, +0.1914]) RR2 size(d=6) - size(d=7) +0.1601 [-0.007863, +0.3838] deg -> CONSISTENT (copy gap -0.01816 [-0.1704, +0.1822]) RR2 size(d=7) - size(d>=8) copies shifted -> CANNOT TELL (copy gap of the difference +0.1356 [+0.0004179, +0.2288]) RR3 this chip: reach edge (unbroken ABOVE from d=3) d>=8; every bin to d>=8 resolved: the kick reaches past d=8 (bins in order: d=3 ABOVE, d=4 ABOVE, d=5 ABOVE, d=6 ABOVE, d=7 ABOVE, d>=8 ABOVE) reach ibm_marrakesh job SYNTH-smooth-5 plan SYNTH coherence: N=0 baseline median 0.636 (all 156 qubits); N=8 idle median 0.629, readout median 0.615; guard threshold 0.0559 (5 x 1/sqrt(8000)) dead-clock guard, units LEFT OUT per bin: d=3 0 of 42, d=4 0 of 38, d=5 0 of 39, d=6 1 of 38, d=7 0 of 38, d>=8 2 of 88, d<=2 1 of 68 RR0 kick per readout, all untouched units, all layouts -0.5356 [-0.6678, -0.4543] deg n=347 -> BELOW (copy gap -0.0137 [-0.06264, +0.03695]) RR1 kick size at d=3 +1.429 [+1.13, +1.621] deg n=42 -> ABOVE (copy gap -0.04258 [-0.1344, +0.1031]) RR1 kick size at d=4 +0.8077 [+0.6814, +1.015] deg n=38 -> ABOVE (copy gap +0.06685 [-0.06507, +0.1807]) RR1 kick size at d=5 +0.6064 [+0.4342, +0.7366] deg n=39 -> ABOVE (copy gap +0.006182 [-0.05402, +0.1323]) RR1 kick size at d=6 +0.4083 [+0.3321, +0.4931] deg n=37 -> ABOVE (copy gap -0.05116 [-0.1566, +0.1329]) RR1 kick size at d=7 +0.231 [+0.1963, +0.2996] deg n=38 -> ABOVE (copy gap +0.01924 [-0.1086, +0.1394]) RR1 kick size at d>=8 +0.1093 [+0.0798, +0.1756] deg n=86 -> ABOVE (copy gap -0.005561 [-0.05916, +0.09405]) RR2 size(d=3) - size(d=4) +0.6209 [+0.2427, +0.8348] deg -> ABOVE (copy gap -0.1094 [-0.2626, +0.06147]) RR2 size(d=4) - size(d=5) +0.2012 [+0.02131, +0.4606] deg -> ABOVE (copy gap +0.06067 [-0.1449, +0.2104]) RR2 size(d=5) - size(d=6) +0.1982 [+0.01457, +0.3361] deg -> ABOVE (copy gap +0.05734 [-0.1377, +0.2459]) RR2 size(d=6) - size(d=7) +0.1773 [+0.07846, +0.2761] deg -> ABOVE (copy gap -0.0704 [-0.2213, +0.1466]) RR2 size(d=7) - size(d>=8) +0.1216 [+0.04168, +0.1922] deg -> ABOVE (copy gap +0.0248 [-0.1458, +0.1633]) RR3 this chip: reach edge (unbroken ABOVE from d=3) d>=8; every bin to d>=8 resolved: the kick reaches past d=8 (bins in order: d=3 ABOVE, d=4 ABOVE, d=5 ABOVE, d=6 ABOVE, d=7 ABOVE, d>=8 ABOVE) RR0 kick per readout, all untouched units, all layouts combined -0.5982 [-0.6652, -0.5311] -> BELOW | chip-to-chip spread chi2/dof 1.17 (dof 2) RR1 kick size at d=3 combined +1.375 [+1.206, +1.544] -> ABOVE | chip-to-chip spread chi2/dof 0.35 (dof 1) RR1 kick size at d=4 combined +0.8964 [+0.7745, +1.018] -> ABOVE | chip-to-chip spread chi2/dof 1.41 (dof 2) RR1 kick size at d=5 combined +0.6433 [+0.5704, +0.7162] -> ABOVE | chip-to-chip spread chi2/dof 1.53 (dof 2) RR1 kick size at d=6 combined +0.4155 [+0.3553, +0.4756] -> ABOVE | chip-to-chip spread chi2/dof 0.10 (dof 2) RR1 kick size at d=7 combined +0.2364 [+0.1904, +0.2824] -> ABOVE | chip-to-chip spread chi2/dof 0.10 (dof 2) RR1 kick size at d>=8 combined +0.143 [+0.1183, +0.1677] -> ABOVE | chip-to-chip spread chi2/dof 3.57 (dof 2) RR2 size(d=3) - size(d=4) combined +0.4737 [+0.2424, +0.7051] -> ABOVE | chip-to-chip spread chi2/dof 2.44 (dof 1) RR2 size(d=4) - size(d=5) combined +0.294 [+0.1523, +0.4357] -> ABOVE | chip-to-chip spread chi2/dof 0.59 (dof 2) RR2 size(d=5) - size(d=6) combined +0.2173 [+0.1129, +0.3216] -> ABOVE | chip-to-chip spread chi2/dof 0.86 (dof 2) RR2 size(d=6) - size(d=7) combined +0.1762 [+0.0947, +0.2578] -> ABOVE | chip-to-chip spread chi2/dof 0.02 (dof 2) RR2 size(d=7) - size(d>=8) combined +0.1266 [+0.05998, +0.1932] -> ABOVE | chip-to-chip spread chi2/dof 0.08 (dof 1) RR3 combined: reach edge (unbroken ABOVE from d=3) d>=8; every bin to d>=8 resolved: the kick reaches past d=8 (bins in order: d=3 ABOVE, d=4 ABOVE, d=5 ABOVE, d=6 ABOVE, d=7 ABOVE, d>=8 ABOVE) TRUTH fez: d=3 +1.551 d=4 +0.921 d=5 +0.681 d=6 +0.415 d=7 +0.260 d>=8 +0.107 TRUTH kingston: d=3 +1.344 d=4 +1.048 d=5 +0.594 d=6 +0.384 d=7 +0.259 d>=8 +0.118 TRUTH marrakesh: d=3 +1.318 d=4 +0.768 d=5 +0.600 d=6 +0.400 d=7 +0.245 d>=8 +0.109 COMBINED vs mean planted: d=3 truth +1.405 read +1.375 [+1.206, +1.544] ABOVE covers | d=4 truth +0.912 read +0.896 [+0.775, +1.018] ABOVE covers | d=5 truth +0.625 read +0.643 [+0.570, +0.716] ABOVE covers | d=6 truth +0.400 read +0.415 [+0.355, +0.476] ABOVE covers | d=7 truth +0.255 read +0.236 [+0.190, +0.282] ABOVE covers | d>=8 truth +0.111 read +0.143 [+0.118, +0.168] ABOVE MISSES ==================================================================================================== NULL FLOOR: six null seeds, no kick planted, every reading (per chip RR0, RR1 x6, RR2 x5; and the same 12 combined) seed 11: per-chip readings 36, ABOVE 0, BELOW 1, CANNOT TELL (copies) 0 | combined 12, ABOVE 1, BELOW 0 | RR3 combined: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size -0.008 [-0.051, +0.035] deg (the bound); ISOLATED ABOVE beyond the edge: d=4 seed 12: per-chip readings 36, ABOVE 1, BELOW 2, CANNOT TELL (copies) 0 | combined 12, ABOVE 0, BELOW 1 | RR3 combined: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size +0.011 [-0.026, +0.048] deg (the bound) seed 13: per-chip readings 36, ABOVE 1, BELOW 1, CANNOT TELL (copies) 3 | combined 12, ABOVE 2, BELOW 0 | RR3 combined: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size -0.003 [-0.036, +0.030] deg (the bound); ISOLATED ABOVE beyond the edge: d=6, d>=8 seed 14: per-chip readings 36, ABOVE 3, BELOW 1, CANNOT TELL (copies) 3 | combined 12, ABOVE 0, BELOW 0 | RR3 combined: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size +0.003 [-0.037, +0.042] deg (the bound) seed 15: per-chip readings 36, ABOVE 1, BELOW 2, CANNOT TELL (copies) 4 | combined 12, ABOVE 0, BELOW 0 | RR3 combined: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size -0.004 [-0.042, +0.033] deg (the bound) seed 16: per-chip readings 36, ABOVE 0, BELOW 0, CANNOT TELL (copies) 8 | combined 12, ABOVE 0, BELOW 0 | RR3 combined: reach edge (unbroken ABOVE from d=3) none; first bin past it d=3 CONSISTENT, size +0.006 [-0.029, +0.041] deg (the bound) FLOOR chip: 13 of 216 readings resolved (6.0 %; 6 above, 7 below) FLOOR comb: 4 of 72 readings resolved (5.6 %; 3 above, 1 below) RR3 under no kick: a reach edge was named on 0 of 18 chip-runs and 0 of 6 combined (the edge needs d=3 ABOVE first)